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CY28341-3
Universal Clock Chip for VIATMP4M/KT/KM400A DDR Systems
Features
* Supports VIA P4M/KM/KT/266/333/400A chipsets * Supports Intel Pentium 4, AthlonTM processors * Supports two DDR DIMMS * Provides: -- Two different programmable CPU clock pairs -- Six differential DDR pairs -- Three low-skew/-jitter AGP clocks -- Seven low-skew/-jitter PCI clocks -- One 48M output for USB -- One programmable 24M or 48M for SIO * Dial-A-Frequency and Dial-A-dB features * Spread Spectrum for best EMI reduction * Watchdog feature for system recovery * SMBus-compatible for programmability * 56-pin SSOP and TSSOP packages Table 1. Frequency Selection Table FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CPU 100.9 100.0 133.9 133.3 110.0 145.2 180.0 198.4 200.9 200.0 166.9 166.6 100.0 133.3 200.0 166.6 AGP 67.3 66.7 66.9 66.7 73.3 72.6 72.0 71.7 66.9 66.7 66.8 66.6 66.7 66.7 66.7 66.6 PCI 33.6 33.3 33.5 33.3 36.7 36.3 36.0 35.8 33.5 33.3 33.4 33.3 33.3 33.3 33.3 33.3
Block Diagram
XIN XOUT XTAL REF0 VDDR REF(0:1) VDDI CPUCS_T/C
FS0
Pin Configuration[1]
SELP4_K7#
VDDC CPU(0:1)/CPU0D_T/C VDDPCI
FS2
PLL1 FS3 FS1
PCI(3:6) PCI_F MULTSEL PCI2 PCI1 VDDAGP AGP(0:2) VDD48M 48M
/2
PD#
SDATA SCLK
SMBus
PLL2 WDEN
24_48M
WD
SRESET# VDDD FBOUT S2D CONVERT DDRT(0:5) DDRC(0:5)
*FS0/REF0 VSSR XIN XOUT VDDAGP AGP0 *SELP4_K7/AGP1 AGP2 VSSAGP **FS1/PCI_F PCI1 *MULTSEL/PCI2 VSSPCI PCI3 PCI4 VDDPCI PCI5 PCI6 VSS48M **FS3/48M **FS2/24_48M VDD48M VDD VSS IREF *PD#/SRESET# SCLK SDATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VTTPWRGD#/REF1 VDDR VSSC CPUT/CPUOD_T CPUC/CPUOD_C VDDC VDDI CPUCS_C CPUCS_T VSSI FBOUT BUF_IN DDRT0 DDRC0 DDRT1 DDRC1 VDDD VSSD DDRT2 DDRC2 DDRT3 DDRC3 VDDD VSSD DDRT4 DDRC4 DDRT5 DDRC5
CY28341-3
Buf_IN
56 pin SSOP
Note: 1. Pins marked with [*] have internal 250 K
pull-up resistors. Pins marked with [**] have internal 250 K
pull-down resistors.
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 19
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CY28341-3
Pin Description[2]
Pin Number 3 4 1 XIN XOUT FS0/REF0 VDDR 56 VTTPWRGD# VDDR I VDD Pin Name PWR I/O I O Pin Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN.
Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS0 state is PU latched and this pin becomes REF0, buffered copy of signal applied at XIN. (1-2 x strength, selectable by SMBus. Default value is 1 x strength.) If SELP4_K7 = 1, with a P4 processor set up as CPUT/C. At power-up, VTT_PWRGD# is an input. When this input transitions to a logic low, the FS (3:0) and MULTSEL are latched and all output clocks are enabled. After the first high to low transition on VTT_PWRGD#, this pin is ignored and will not effect the behavior of the device thereafter. When the VTT_PWRGD# feature is not used, please connect this signal to ground through a 10K resistor. If SELP4_K7 = 0, with an Athlon (K7) processor as CPU_OD(T:C). VTT_PWRGD# function is disabled, and the feature is ignored. This pin becomes REF1 and is a buffered copy of the signal applied at XIN. DDR Clock Outputs. DDR Clock Outputs.
REF1 VDDR 44,42,38, 36,32,30 43,41,37 35,31,29 7 DDRT (0:5) DDRC (0:5) SELP4_K7 / AGP1 VDDD VDDD O O O
Power-on Bidirectional Input/Output. At power-up, SELP4_K7 is the input. I/O When the power supply voltage crosses the input threshold voltage, VDDAGP PU SELP4_K7 state is latched and this pin becomes AGP1 clock output. SELP4_K7 = 1, P4 mode. SELP4_K7 = 0, K7 mode. VDDPCI Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input. I/O When the power supply voltage crosses the input threshold voltage, MULTSEL PU state is latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is 4 x IREFMULTSEL = 1, Ioh is 6 x IREF O 3.3V CPU Clock Outputs. This pin is programmable through strapping pin7, SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUT Clock Output. If SELP4_K7 = 0, this pin is configured as the CPUOD_T Open Drain Clock Output. See Table 1 3.3V CPU Clock Outputs. This pin is programmable through strapping pin7, SELP4_K7. If SELP4_K7 = 1, this pin is configured as the CPUC Clock Output. If SELP4_K7 = 0, this pin is configured as the CPUOD_C Open Drain Clock Output. See Table 1 2.5V CPU Clock Outputs for Chipset. See Table 1. PCI Clock Outputs. Are synchronous to CPU clocks. See Table 1
12
MULTSEL/PCI2
53
CPUT/CPUOD_T VDDC
52
CPUC/CPUOD_C VDDC O O O
48,49 10
CPUCS_T/C FS1/PCI_F
VDDI VDDPCI VDDPCI
14,15,17,18 PCI (3:6)
Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS1 state is PD latched and this pin becomes PCI_F clock output. Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS3 state is PD latched and this pin becomes 48M, a USB clock output. I/O PCI Clock Output. PD Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When I/O the power supply voltage crosses the input threshold voltage, FS2 state is PD latched and this pin becomes 24_48M, a SIO programmable clock output. O O AGP Clock Output. Is synchronous to CPU clocks. See Table 1. AGP Clock Output. Is synchronous to CPU clocks. See Table 1.
(range 200 K to 500 K ).
20
FS3/48M VDD48M
11 21
PCI1 FS2/24_48M
VDDPCI VDD48M
6 8
AGP0 AGP2
VDDAGP VDDAGP
Note: 2. PU = internal pull-up. PD = internal pull-down. Typically = 250 K
Rev 1.0, November 21, 2006
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CY28341-3
Pin Description[2] (continued)
Pin Number 25 28 Pin Name IREF SDATA PWR I/O I Pin Description Current reference programming input for CPU buffers. A precise resistor is attached to this pin, which is connected to the internal current reference.
Serial Data Input. Conforms to the Phillips I2C specification of a Slave I/O Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. I Serial Clock Input. Conforms to the Philips I2C specification. Power-down Input/System Reset Control Output. If Byte6 Bit7 = 0(default), this pin becomes a SRESET# open drain output. See system reset description. I/O If Byte6Bit7 = 1, this pin becomes PD# input with an internal pull-up. When PU PD# is asserted low, the device enters power down mode. See power management function. Input to DDR Differential Buffers. 2.5V single-ended SDRAM buffered output of the signal applied at BUF_IN. 3.3V power supply for AGP clocks. 3.3V power supply for CPUT/C clocks. 3.3V power supply for PCI clocks. 3.3V power supply for REF clock. 2.5V power supply for CPUCS_T/C clocks. 3.3V power supply for 48M. 3.3V Common power supply. 2.5V power supply for DDR clocks. Ground for AGP clocks. Ground for PCI clocks. Ground for CPUT/C clocks. Ground for DDR clocks. Ground for 48M clock. Ground for CPUCS_T/C clocks. Ground for REF. Common Ground.
27 26
SCLK PD#/SRESET#
45 46 5 51 16 55 50 22 23 34,40 9 13 54 33,39 19 47 2 24
BUF_IN FBOUT VDDAGP VDDC VDDPCI VDDR VDDI VDD_48M VDD VDDD VSSAGP VSSPCI VSSC VSSD VSS_48M VSSI VSSR VSS
Power Management Functions
All clocks can be individually enabled or stopped via the two-wire control interface. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stop and on transitions from stopped to running when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within about 0.5 mS.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
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CY28341-3
Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave ...................... Data Byte (N-1) -8 bits Acknowledge from slave Data Byte N -8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Byte Read Protocol Description Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge from master Data byte from slave - 8 bits Acknowledge from master Data byte from slave - 8 bits Acknowledge from master Data byte N from slave - 8 bits Acknowledge from master Stop Block Read Protocol Description
19 20:27 28
19 20 21:27
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CY28341-3
Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit 29 Stop Description Bit 28 29 30:37 38 39 Read = 1 Acknowledge from slave Data byte from slave - 8 bits Acknowledge from master Stop Byte Read Protocol Description
Serial Control Registers
Byte 0: Frequency Select Register Bit 7 6 5 4 3 @Pup 0 H/W Setting H/W Setting H/W Setting 0 21 10 1 Pin# Name Reserved FS2 FS1 FS0 FS_Override Reserved For Selecting Frequencies in Frequency Selection Table on page 1 For Selecting Frequencies in Frequency Selection Table on page 1 For Selecting Frequencies in Frequency Selection Table on page 1 If this bit is programmed to "1", it enables WRITE to bits (6:4,1) for selecting the frequency via software (SMBus) If this bit is programmed to a "0" it enable only READ of bits (6:4,1), which reflect the hardware setting of FS(0:3). Reserved, set = 0 For Selecting frequencies in Frequency Selection Table on page 1 Only for reading the hardware setting of the CPU interface mode, status of SELP4_K7# strapping. Description
2 1 0
0 H/W Setting H/W Setting
11 20 7
Reserved FS3 SELP4_K7
Byte 1: CPU Clocks Register Bit 7 6 5 4 3 2 1 @Pup 0 1 1 1 1 1 0 Pin# MODE SSCG SST1 SST0 48,49 CPUCS_T, CPUCS_C 53,52 CPUT/CPUOD_T CPUC/CPUOD_C 53,52 CPUT/C Name Description 0 = Down Spread. 1 = Center Spread. See Table 9 on page 8 1 = Enable (default). 0 = Disable Select spread bandwidth. See Table 9 on page 8 Select spread bandwidth. See Table 9 on page 8 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disable. In K7 mode, this bit is ignored.In P4 mode, 0 = when PD# asserted LOW, CPUT stops in a high state, CPUC stops in a low state. In P4 mode, 1 = when PD# asserted LOW, CPUT and CPUC stop in High-Z. Only for reading the hardware setting of the Pin11 MULT0 value.
0
1
11
MULT0
Byte 2: PCI Clock Register Bit 7 6 5 4 3 @Pup 0 1 1 1 1 10 18 17 15 Pin# Name PCI_DRV PCI_F PCI6 PCI5 PCI4 Description PCI clock output drive strength 0 = Low strength, 1 = High strength 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state.
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CY28341-3
Byte 2: PCI Clock Register (continued) 2 1 0 1 1 1 14 12 11 PCI3 PCI2 PCI1 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state.
Byte 3: AGP/Peripheral Clocks Register Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 0 0 1 1 1 Pin# 21 20 21 6,7,8 6,7,8 8 7 6 Name 24_48M 48MHz 24_48M DASAG1 DASAG0 AGP2 AGP1 AGP0 Description 0 = pin21 output is 24MHz. Writing a '1' into this register asynchronously changes the frequency at pin21 to 48 MHz. 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low Programming these bits allow shifting skew of the AGP(0:2) signals relative to their default value. See Table 5. 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low
Table 5. Dial-a-Skew DASAG (1:0) 00 01 10 11
AGP(0:2) AGP(0:2) Skew Shift Default -280 ps +280 ps +480 ps
Byte 4: Peripheral Clocks Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 1 1 1 1 Pin# 20 21 6,7,8 6,7,8 1 56 1 56 48M 24_48M DARAG1 DARAG0 REF0 REF1 REF0 REF1 Name Description 1 = Low strength, 0 = High strength 1 = Low strength, 0 = High strength Programming these bits allow modifying the frequency ratio of the AGP(2:0), PCI(6:1, F) clocks relative to the CPU clocks. See Table 6. 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = output enabled (running). 0 = output disabled asynchronously in a low 1 = Low strength, 0 = High strength 1 = Low strength, 0 = High strength (K7 Mode only)
Table 6. Dial-A-Ratio DARAG (1:0) 00 01 10 11
AGP(0:2) CU/AGP Ratio Frequency Selection Default 2/1 2.5/1 3/1
Byte 5: SDR/DDR Clock Register Bit 7 @Pup 0 Pin# 45 Name BUF_IN threshold voltage FBOUT DDRT/C5 Description DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05V
6 5
1 1
46 29,30
1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state.
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CY28341-3
Byte 5: SDR/DDR Clock Register (continued) Bit 4 3 2 1 0 @Pup 1 1 1 1 1 Pin# 31,32 35,36 37,38 41,42 43,44 Name DDRT/C4 DDRT/C3 DDRT/C2 DDRT/C1 DDRT/C0 Description 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 = output enabled (running). 0 = output disabled asynchronously in a low state.
Byte 6: Watchdog Register Bit 7 @Pup 0 Pin# 26 Name SRESET# Description 1 = Pin 26 is the input pin as PD# signal. 0 = Pin 26 is the output pin as SRESET# signal. This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time out only. 0 = select frequency of existing H/W setting, 1 = select frequency of the second to last S/W table setting. (the software setting prior to the one that caused a system reboot). For IMI Test - WD-Test, ALWAYS program to '0' This bit is set to "1" when the Watchdog times out. It is reset to "0" when the system clears the WD time stamps (WD3:0). This bit allows the selection of the time stamp for the Watchdog timer. See Table 7 This bit allows the selection of the time stamp for the Watchdog timer. See Table 7 This bit allows the selection of the time stamp for the Watchdog timer. See Table 7 This bit allows the selection of the time stamp for the Watchdog timer. See Table 7
6 5 4 3 2 1 0
0 0 0 0 0 0 0
Frequency Revert WDTEST WD Alarm WD3 WD2 WD1 WD0
Table 7. Watchdog Time Stamp WD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Off 1 second 2 seconds 3 seconds 4 seconds 5 seconds 6 seconds 7 seconds 8 seconds 9 seconds 10 seconds 11 seconds 12 seconds 13 seconds 14 seconds 15 seconds FUNCTION
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CY28341-3
Byte 7: Dial-a-Frequency Control Register N Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# Name Reserved N6, MSB N5 N4 N3 N2 N3 N0, LSB Description Reserved for device function test. These bits are for programming the PLL's internal N register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock.
Byte 8: Silicon Signature Register (all bits are read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Pin# Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor_ID1 Vendor_ID0 Revision ID bit [3] Revision ID bit [2] Revision ID bit [1] Revision ID bit [0] Cypress's Vendor ID bit [3]. Cypress's Vendor ID bit [2]. Cypress's Vendor ID bit [1]. Cypress's Vendor ID bit [0]. Description
Byte9: Dial-A-Frequency Control Register R Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# Name Reserved R5, MSB R4 R3 R2 R1 R0 DAF_ENB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is load from DAF (SMBus) registers. Table 9. Spread Spectrum Table Mode 0 0 0 0 FS(4:0) XXXXX P 96016000 1 1 1 1 SST1 0 0 1 1 0 0 1 1 SST0 0 1 0 1 0 1 0 1 % Spread -1.5% -1.0% -0.7% -0.5% 0.75% 0.5% 0.35% 0.25% Reserved These bits are for programming the PLL's internal R register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description
Dial-A-Frequency Feature
SMBus Dial-a-Frequency feature is available in this device via Byte7 and Byte9. P is a PLL constant that depends on the frequency selection prior to accessing the Dial-a-Frequency feature. Table 8.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is enabled/disabled via SMBus register Byte 1, Bit 7.
Rev 1.0, November 21, 2006
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CY28341-3
Swing Select Functions Through Hardware
MULTSEL 1 Board Target Trace/Term Z 50 Ohm Reference R, IREF = VDD/(3*Rr) Rr = 475 1%, IREF = 2.32mA Output Current IOH = 6* Iref VOH@Z 0.7V@50
Watchdog Self-Recovery Sequence
This feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang-up due to the frequency change. When the system sends an SMBus command requesting a frequency change through the Dial-a-Frequency Control Registers, it must have previously sent a command to the Watchdog timer to select which time-out stamp the Watchdog must perform, otherwise the System Self-Recovery feature will not be applicable. Consequently, this device will change frequency and then the Watchdog timer starts timing.
Meanwhile, the system BIOS is running its operation with the new frequency. If this device receives a new SMBus command to clear the bits originally programmed in the Watchdog timer bits (reprogram to 0000) before the Watchdog times out, then this device will keep operating in its normal condition with the new selected frequency. The Watchdog timer will also be triggered if you program the software frequency select bits (FSEL) to a new frequency selection. If the Watchdog times out before the new SMBus reprograms the Watchdog timer bits to (0000), then this device send a low system reset pulse, on SRESET# and changes Watchdog time-out bit to "1".
W AT C H D O G T IM E R P R O G R AM M IN G
R E S E T W AT C H D O G T IM E R S et W D T im er B its = 0 C l ear W D A lar m bit = 0
IN IT IAL IZ E W AT C H D O G T IM E R S et F r eq uenc y R ever t B it S et W D T im er B its
C H AN G E F R E Q B Y S E T S O F T W AR E F S E L S et S W F r eq _S el bi ts S et F S over r ide bit
C H AN G E F R E Q B Y S E T D IAL - A- R AT IO S el ec t a differ ent divider r atio
C H AN G E F R E Q B Y S E T D IAL - AF R EQU EN C Y Load M and N R eg i s ter s S et P r o_F r eq _E N = 1
C O U N T D O W N W D T IM E R S end 3m s R es et P ul s e
NO
W D T im er = 0
C L E AR W D T IM E R S et W D A lar m = 1
F req u en cy R ev ert B it = 0 S et F r eq uenc y to F S _H W _Latc hed
F req u en cy R ev ert B it = 1 S et F r eq uenc y to F S _S W S etti ng
S R E S E T # = 0 f o r 3 m sec
R eset & R ev ert F req u en cy b ack
Figure 1. Watchdog Self Recovery Sequence Flowchart
Rev 1.0, November 21, 2006
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CY28341-3
P4 Processor SELP4_K7# = 1 Power-down Assertion (P4 Mode) When PD# is sampled low by two consecutive rising edges of CPU# clock then all clock outputs except CPU clocks must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. Note that Figure 1 shows CPU = 133 MHz. This diagram and description are applicable for all valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Power-down Deassertion (P4 Mode) The power-up latency needs to be less than 3 mS. AMD K7 processor SELP4_K7# = 0 Power-down Assertion (K7 Mode) When the PD# signal is asserted low, all clocks are disabled to a low level in an orderly fashion prior to removing power from the part. When PD# is asserted (forced) low, the device transitions to a shutdown (power down) mode and all power supplies may then be removed. When PD# is sampled low by two consecutive rising edges of CPU clock, then all affected clocks are stopped in a low state as soon as possible. When in power down (and before power is removed), all outputs are synchronously stopped in a low state (see Figure 3 below), all PLL's are shut off, and the crystal oscillator is disabled. When the device is shutdown, the I2C function is also disabled.
PD# C P U T 1 33 M H z C P U C 1 33 M H z P C I 33 M H z A G P 66 M H z U S B 48 M H z R E F 1 4.3 18 M H z D D R T 1 33 M H z D D R C 1 33 M H z
Figure 2. Power-down Assertion Timing Waveform (in P4 Mode)
< 1 .5 m sec PD# CPUT 133M Hz CPUC 133M Hz PCI 33M Hz AG P 66M Hz USB 48M Hz R E F 1 4 .3 1 8 M H z DDRT 133M Hz DDRC 133M Hz
Figure 3. Power-down Deassertion Timing Waveform (in P4 mode)
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PD# CPUOD_T 133MHz CPUCS_T 133MHz CPUOD_C 133MHz CPUCS_C 133MHz PCI 33MHz AGP 66MHz USB 48MHz REF 14.318MHz DDRT 133MHz DDRC 133MHz
Figure 4. Power-down Assertion Timing Waveform (In K7 Mode)
Power-down Deassertion (K7 Mode) When deasserted PD# to high level, all clocks are enabled and start running on the rising edge of the next full period in order to guarantee a glitch free operation, no partial clock pulses.
<1.5 m sec PD# C P U T 133 M H z C P U C 133 M H z P C I 33 M H z A G P 66 M H z U S B 4 8M H z R E F 14.318 M H z D D R T 133 M H z D D R C 13 3M H z
Figure 5. Power-down Deassertion Timing Waveform (in K7 Mode) Rev 1.0, November 21, 2006 Page 11 of 19
CY28341-3
VID (0:3), SEL (0,1) VTT_PW RGD# PW RGD
VDD Clock Gen Clock State State 0
0.2-0.3m S Delay State 1
W ait for VTT_GD#
Sam ple Sels State 2 State 3 (See Note 3)
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 6. VTT_PWGD# Timing Diagram (with P4 Mode, SelP4_K7 = 1)[3]
WR TP
S1
=L
ow
GD
#
S2
D e la y 0 .2 5 m S
S a m p le In p u ts F S ( 3 :0 )
W a it f o r 1 .1 4 6 m s
VT
E n a b le O u tp u te s
V D D A = 2 .0 V
S0
S3
P o w e r O ff
V D D 3 .3 = O f f
N o rm a l O p e r a tio n
Figure 7. Clock Generator Power-up/Run State Diagram (with P4 Processor SELP4_K7#=1) Connection Circuit DDRT/C Signals For open-drain CPU output signals (with K7 processor SELP4_K7#=0)
3.3V Ohm CPUOD_T 47 Ohm Ohm 5" 680 pF 3.3V 301 Ohm 47 Ohm CPUOD_C Ohm Ohm 5" 680 pF 60.4 Ohm 500 Ohm VDDCPU(1.5V) 20 pF VDDCPU(1.5V) Ohm 1" 500 Ohm 500 Ohm VDDCPU(1.5V) 60.4 Ohm Ohm " 20 pF VDDCPU(1.5V) 500 Ohm
Measurement Point
Measurement Point
Figure 8. K7 Load Termination
Note: 3. This time diagram shows that VTT_PWRGD# transits to a logic low in the first time at power-up. After the first high-to-low transition of VTT_PWRGD#, device is not affected, VTT_PWRGD# is ignored.
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CY28341-3
6"
6"
Figure 9. CS Load Termination
DDRT
60 16 pF 120 60 16 pF
Measurement Point
DDRC
Measurement Point
Figure 10. DDR Termination Table 10.Signal Loading Table Clock Name REF, 48MHz (USB), 24_48MHz AGP PCI_F DDRT/C, FBOUT CPUT/C CPUOD_T/C CPUCS_T/C Max Load (pF) 20 30 30 16 See Figure 11 See Figure 8 See Figure 9 For Differential CPU Output Signals (with P4 Processor SELP4_K7= 1) The following diagram shows lumped test load configurations for the differential Host Clock outputs.
T PCB
VD D CPU T
2pF
M e a su re m e n t P o in t
MU LTSEL
T PCB
CPUC
2pF
M e a su re m e n t P o in t
Figure 11. P4 0.7V Termination Table 11.Group Timing Relationships and Tolerances[4] Offset (ps) tCSAGP CPUCS to AGP 750 Tolerance (ps) 500 Conditions CPUCS Leads
AGP to PCI 1,250 500 AGP Leads tAP Note: 4. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), the same length of transmission line should be added to the other signal of the pair (e.g., AGP).
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CY28341-3
0ns 10ns 20ns 30ns
CPU CLOCK 66.6MHz CPU CLOCK 100MHz CPU CLOCK 133.3MHz tCSAGP AGP CLOCK 66.6MHz tAP PCI CLOCK 33.3MHz
Figure 12. Group Timing Relationships
Rev 1.0, November 21, 2006
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CY28341-3
Absolute Maximum Conditions
Parameter VDD VDDA VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Relative to V SS Non-functional Functional MIL-STD-883, Method 3015 Mil-STD 883E, Method 1012.1 TSSOP SSOP TSSOP SSOP Flammability Rating Moisture Sensitivity Level At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - 2000 20.92 38.62 75.18 69.97 V-0 1 Max. 4.6 4.6 VDD + 0.5 +150 70 150 - Unit V V VDC C C C V C/W
Temperature, Operating Ambient Functional
Dissipation, Junction to Ambient JEDEC (JESD 51)
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power-supply sequencing is NOT required.
DC Electrical Specifications (VDD=VDDPCI=VDDAGP=VDDR=VDD48M=VDDC= 3.3v5%, VDDI = VDD=2.55%, TA=0C TO +70C)
Parameter VIL1 VIH1 VIL2 VIH2 VOL LOL IOZ Idd3.3V Idd2.5V IPD IPUP IPDWN CIN COUT LPIN CXTAL Description Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage for SRESET# Pull-down current for SRESET# Three-state leakage Current Dynamic Supply Current Dynamic Supply Current Power Down Supply current Internal Pull-up Device Current Internal Pull-down Device Current Input pin capacitance Output pin capacitance Pin Inductance Crystal pin capacitance Conditions Applicable to PD#, F S(0:4) Applicable to SDATA and SCLK IOL VOL = 0.4V CPU frequency set at 133.3 MHz, Note 5 CPU frequency set at 133.3 MHz, Note 5 PD# = 0 Input @ VSS Input @ VDD Min. - 2.0 - 2.2 0.4 24 - - - - - - - - - 27 Typ. - - - - - 35 - 150 175 95 - - - - - 36 Max. 0.8 - 1.0 - - - 10 190 195 600 -25 10 5 6 7 45 Unit Vdc Vdc Vdc Vdc V mA A mA mA A A A pF pF pF pF
Measured from the Xin or Xout to VSS
AC Parameters
Parameter XTAL TDC TPERIOD VHIGH VLOW TR/TF TCCJ Txs Description Xin Duty Cycle Xin Period Xin High Voltage Xin Low Voltage Xin Rise and Fall Times Xin Cycle to Cycle Jitter Crystal Start-up Time 100 MHz Min. Max. 45 69.841 .7VDD 0 - - 55 71.0 VDD .3VDD 10.0 500 30 133MHz Min. Max 45 69.84 .7VDD 0 - - 55 71.0 VDD .3VDD 10 500 30 200 MHz Min. Max. 45 69.84 .7VDD 0 - - 55 71.0 VDD .3VDD 10 500 30 Unit % ns V V ns ps ms Notes 6,17 6,17 15 15 16 7,14 13,15
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CY28341-3
AC Parameters (continued)
100 MHz Parameter Description Min. Max. P4 Mode CPU at 0.7V TDC CPUT/C Duty Cycle 45 55 TPERIOD CPUT/C Period 9.997 10.003 CPUT/C Rise and Fall Times 175 1300 TR/TF Rise/Fall Matching - 20% Rise/Fall Time Variation - 125 TR/TF CPUCS_T/C to CPUT/C Clock Skew - 100 TSKEW CPUT/C Cycle to Cycle Jitter - 250 TCCJ VCROSS Crossing Point Voltage at 0.7V Swing 250 550 K7 Mode TDC CPUOD_T/C Duty Cycle 45 55 CPUOD_T/C Period 9.997 10.003 TPERIOD CPUOD_T/C Low Time 2.8 - TLOW CPUOD_T/C Fall Time 0.4 1.6 TF CPUCS_T/C to CPUODT/C Clock - 100 TSKEW Skew TCCJ CPUOD_T/C Cycle-to-Cycle Jitter - 150 Differential Voltage AC .4 Vp+.6V VDIFF Differential Crossover Voltage 0.5*VDD 0.5*VDDC VCROSS +0.1 C-0.1 CHIPSET CLOCK TDC CPUCS_T/C Duty Cycle 40 60 CPUCS_T/C Period 9.997 10.003 TPERIOD T R / TF CPUCS_T/C Rise and Fall Times 0.4 1.6 Differential Voltage AC .4 Vp+.6V VDIFF Differential Crossover Voltage 0.5*VDD 0.5*VDDI+ VCROSS 0.8 I-0.8 AGP TDC AGP Duty Cycle 45 55 AGP Period 15 15.3 TPERIOD AGP High Time 4.95 - THIGH AGP Low Time 4.55 - TLOW AGP Rise and Fall Times 0.5 2.0 T R / TF TSKEW Any AGP to Any AGP Clock Skew - 250 AGP Cycle-to-Cycle Jitter - 500 TCCJ PCI TDC PCI_F Duty Cycle 45 55 TPERIOD PCI_F Period 30.0 - PCI_F High Time 12.0 - THIGH PCI_F Low Time 12.0 - TLOW PCI_F Rise and Fall Times 0.5 2.0 T R / TF Any PCI to Any PCI Clock Skew - 500 TSKEW PCI_F Cycle-to-Cycle Jitter - 500 TCCJ 48 MHz TDC 48-MHz Duty Cycle 45 55 48-MHz Period 20.8299 20.8333 TPERIOD 48-MHz Rise and Fall Times 1.0 2.0 T R / TF 48-MHz Cycle-to-Cycle Jitter - 350 TCCJ Rev 1.0, November 21, 2006 133MHz Min. Max 45 7.4978 175 - - - - 250 45 7.4978 1.67 0.4 - 55 7.5023 1300 20% 125 100 250 550 55 7.5023 - 1.6 100 200 MHz Min. Max. 45 4.9985 175 - - - - 250 45 4.9985 2.8 0.4 - Unit Notes 6,7,9,20,23 6,7,9,20,23 22 22,25 7,22,23 7,10,20,23 7,10,20,23 23 7,9 7,9 7,9 7,8 7,10,20
55 % 5.0015 ns 1300 ps 20% 125 ps 100 ps 250 ps 550 mV 55 5.0015 - 1.6 100 % ns ns ns 0
- 150 - 150 ps 7,9 .4 Vp+.6V .4 Vp+.6V V 19 0.5*VDD 0.5*VDD 0.5*VDD 0.5*VDD mV 18 C-0.1 C+0.1 C-0.1 C+0.1 40 60 40 60 % 6,7,9 7.4978 7.5023 4.9985 5.0015 ns 6,7,9 0.4 1.6 0.4 1.6 ns 6,7,8 .4 Vp+.6V .4 Vp+.6V V 21 0.5*VDD 0.5*VDD 0.5*VDD 0.5*VDD V 20 I-0.8 I+0.8 I-0.8 I+0.8 45 15 4.95 4.55 0.5 - - 45 30.0 12.0 12.0 0.5 - - 55 15.3 - - 2.0 250 500 55 - - - 2.0 500 500 45 15 4.95 4.55 0.5 - - 45 30.0 12.0 12.0 0.5 - - 55 15.3 - - 2.0 250 500 55 - - - 2.0 500 500 % ns ns ns ns ps ps % ns ns ns ns ps ps 6,7,9 6,7,9 7,11 7,12 7,8 7,10 7,9,10 6,7,9 6,7,9 7,11 7,12 7,27 7,10 7,9,10
45 55 45 55 % 6,7,9 20.8299 20.8333 20.8299 20.8333 ns 6,7,9 1.0 2.0 1.0 2.0 ns 7,8 - 350 - 350 ps 7,9,10
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CY28341-3
AC Parameters (continued)
Parameter 24 MHz TDC TPERIOD T R / TF TCCJ REF TDC TPERIOD T R / TF TCCJ DDR VX VD TDC TPERIOD TR/TF TSKEW TCCJ THPJ TDELAY TSKEW TSTABLE Description 24-MHz Duty Cycle 24-MHz Period 24-MHz Rise and Fall Times 24-MHz Cycle-to-Cycle Jitter REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle-to-Cycle Jitter 100 MHz Min. Max. 45 41.660 1.0 - 45 69.8413 1.0 - 55 41.667 4.0 500 55 71.0 4.0 1000 133MHz Min. Max 45 41.660 1.0 - 45 69.8413 1.0 - 55 41.667 4.0 500 55 71.0 4.0 1000 200 MHz Min. Max. 45 41.660 1.0 - 45 69.8413 1.0 - 55 41.667 4.0 500 55 71.0 4.0 1000 0.5*VDD D+0.2 VDDD + 0.6 55 5.0015 3 100 150 100 4 100 3 Unit % ns ns ps % ns ns ps Notes 6,7,9 6,7,9 7,8 7,9,10 6,7,9 6,7,9 7,8 7,9,10
Crossing Point Voltage of DDRT/C 0.5*VDD 0.5*VDDD 0.5*VDD +0.2 D-0.2 D-0.2 Differential Voltage Swing 0.7 VDDD + 0.7 0.6 DDRT/C(0:5) Duty Cycle 45 55 45 DDRT/C(0:5) Period 9.997 10.003 7.4978 DDRT/C(0:5) Rise/Fall Slew Rate 1 3 1 DDRT/C to any DDRT/C Clock - 100 - Skew DDRT/C(0:5) Cycle-to-Cycle Jitter - 150 - DDRT/C(0:5) Half-period Jitter - 100 - BUF_IN to Any DDRT/C Delay 1 4 1 FBOUT to Any DDRT/C Skew - 100 - All-Clock Stabilization from Power-up - 3 -
0.5*VDD 0.5*VDD D+0.2 D-0.2 VDDD + 0.7 0.6 55 45 7.5023 4.9985 3 1 100 - 150 100 4 100 3 - - 1 - -
V 18 V 19 % ns V/ns ps ps ps ns ps ms 20 20 8 7,10,20 7,10,20 7,10,20 7,9 7,9 13
Notes: 5. All outputs loaded as per maximum capacitive load table. 6. This parameter is measured as an average over a 1-us duration, with a crystal center frequency of 14.31818 MHz. 7. All outputs loaded as per loading specified in Table 11. 8. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V signals and between 20% and 80% for differential signals. 9. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V and 50% point for differential signals. 10. This measurement is applicable with Spread ON or spread OFF. 11. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals). 12. Probes are placed on the pins, and measurements are acquired at 0.4V. 13. The time specified is measured from when all VDDs reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within the specifications. 14. When Xin is driven from and external clock source (3.3V parameters apply). 15. When crystal meets minimum 40-ohm device series resistance specification. 16. Measured between 0.2VDD and 0.7VDD. 17. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within data sheet specifications. 18. The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same. 19. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary DDRC (and CPUCS_C) one. 20. Measured at VX, or where subtraction of CLK-CLK# crosses 0V. 21. Measured at VX between the rising edge and the following falling edge of the signal. 22. Measured from Vol = 0.175V to Voh = 0.525V. 23. See Figure 11 for 0.7V loading specification. 24. Measurement taken from differential waveform, from -0.35V to +0.35V. 25. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as "the instantaneous difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time". This parameter is designed for waveform symmetry. 26. Measured in absolute voltage, i.e., single-ended measurement. 27. Probes are placed on the pins, and measurements are acquired between 0.8V and 2.0V signals and between 20% and 80% for differential signals.
Rev 1.0, November 21, 2006
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CY28341-3
Ordering Information
Part Number CY28341OC-3 CY28341OC-3T CY28341ZC-3 CY28341ZC-3T Package Type 56-pin Shrunk Small Outline package (SSOP) 56-pin Shrunk Small Outline package (SSOP)-Tape and Reel 56-pin Thin Shrunk Small Outline package(TSSOP) 56-pin Thin Shrunk Small Outline package(TSSOP)-Tape and Reel Product Flow Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C
Package Drawing and Dimensions
56-pin Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
51 85060 B*
Rev 1.0, November 21, 2006
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CY28341-3
56-Lead Shrunk Small Outline Package O56
51-85062-*C
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 21, 2006
Page 19 of 19

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